Description:

MIPS processor of the Nintendo 64. The R4300i is a 64-bit processor. It supports the MIPS III ISA introduction set.

CPU clock speed:

93.75 MHz

Address bus:

32-Bit

CPU caches:

Document version:

1.0.0

Sources:

• https://github.com/martinlindhe/n64ops
• https://www.copetti.org/writings/consoles/nintendo-64

Opcode:

32

Format:

LB rt, offset(base)

Purpose:

To load a byte from memory as a signed value.

Implementation:

rt = byte[base+offset]

How to decode:

Opcode:

36

Format:

LBU rt, offset(base)

Purpose:

To load a byte from memory as an unsigned value.

Implementation:

rt = byte[base+offset]

How to decode:

Opcode:

55

Format:

LD rt, offset(base)

Purpose:

To load a doubleword from memory.

Implementation:

rt = doubleword[base+offset]

How to decode:

Opcode:

26

Format:

LDL rt, offset(base)

Purpose:

To load the most-significant part of a doubleword from an unaligned memory address.

Implementation:

left(rt) = right[base+offset]

How to decode:

Opcode:

27

Format:

LDR rt, offset(base)

Purpose:

To load the least-significant part of a doubleword from an unaligned memory address.

Implementation:

right(rt) = left[base+offset]

How to decode:

Opcode:

33

Format:

LH rt, offset(base)

Purpose:

To load a halfword from memory as a signed value.

Implementation:

rt = halfword[base+offset]

How to decode:

Opcode:

37

Format:

LHU rt, offset(base)

Purpose:

To load a halfword from memory as an unsigned value.

Implementation:

rt = halfword[base+offset]

How to decode:

Opcode:

48

Format:

LL rt, offset(base)

Purpose:

To load a word from memory for an atomic read-modify-write.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

52

Format:

LLD rt, offset(base)

Purpose:

To load a doubleword from memory for an atomic read-modify-write.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

35

Format:

LW rt, offset(base)

Purpose:

To load a word from memory as a signed value.

Implementation:

rt = word[base+offset]

How to decode:

Opcode:

34

Format:

LWL rt, offset(base)

Purpose:

To load the most-significant part of a word as a signed value from an unaligned memory address.

Implementation:

left(rt) = right[base+offset]

How to decode:

Opcode:

38

Format:

LWR rt, offset(base)

Purpose:

To load the least-significant part of a word from an unaligned memory address as a signed value.

Implementation:

right(rt) = left[base+offset]

How to decode:

Opcode:

39

Format:

LWU rt, offset(base)

Purpose:

To load a word from memory as an unsigned value.

Implementation:

rt = word[base+offset]

How to decode:

Opcode:

40

Format:

SB rt, offset(base)

Purpose:

To store a byte to memory.

Implementation:

byte[base+offset] = rt

How to decode:

Opcode:

56

Format:

SC rt, offset(base)

Purpose:

To store a word to memory to complete an atomic read-modify-write.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

60

Format:

SCD rt, offset(base)

Purpose:

To store a doubleword to memory to complete an atomic

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

63

Format:

SD rt, offset(base)

Purpose:

To store a doubleword to memory.

Implementation:

doulbeword[base+offset] = rt

How to decode:

Opcode:

44

Format:

SDL rt, offset(base)

Purpose:

To store the most-significant part of a doubleword to an unaligned memory address.

Implementation:

right[base+offset] = left(rt)

How to decode:

Opcode:

45

Format:

SDR rt, offset(base)

Purpose:

To store the least-significant part of a doubleword to an unaligned memory address.

Implementation:

left[base+offset] = right(rt)

How to decode:

Opcode:

41

Format:

SH rt, offset(base)

Purpose:

To store a halfword to memory.

Implementation:

halfword[base+offset] = rt

How to decode:

Opcode:

43

Format:

SW rt, offset(base)

Purpose:

To store a word to memory.

Implementation:

word[base+offset] = rt

How to decode:

Opcode:

42

Format:

SWL rt, offset(base)

Purpose:

To store the most-significant part of a word to an unaligned memory address.

Implementation:

right[base+offset] = left(rt)

How to decode:

Opcode:

46

Format:

SWR rt, offset(base)

Purpose:

To store the least-significant part of a word to an unaligned memory address.

Implementation:

left[base+offset] = right(rt)

How to decode:

Opcode:

0

Format:

SYNC (stype = 0 implied)

Purpose:

To order loads and stores to shared memory in a

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

0

Format:

ADD rd, rs, rt

Purpose:

To add 32-bit integers. If overflow occurs, then trap. Comment: ADD rd, r0, rs is equal to a MOVE rd, rs

Implementation:

rd = rs + rt

How to decode:

Opcode:

8

Format:

ADDI rt, rs, immediate

Purpose:

To add a constant to a 32-bit integer. If overflow occurs, then trap.

Implementation:

rt = rs + immediate

How to decode:

Opcode:

9

Format:

ADDIU rt, rs, immediate

Purpose:

To add a constant to a 32-bit integer.

Implementation:

rt = rs + immediate

How to decode:

Opcode:

0

Format:

ADDU rd, rs, rt

Purpose:

To add 32-bit integers.

Implementation:

rd = rs + rt

How to decode:

Opcode:

0

Format:

AND rd, rs, rt

Purpose:

To do a bitwise logical AND.

Implementation:

rd = (rs AND rt)

How to decode:

Opcode:

12

Format:

ANDI rt, rs, immediate

Purpose:

To do a bitwise logical AND with a constant.

Implementation:

rt = (rs AND immediate)

How to decode:

Opcode:

0

Format:

DADD rd, rs, rt

Purpose:

To add 64-bit integers. If overflow occurs, then trap.

Implementation:

rd = rs + rt

How to decode:

Opcode:

24

Format:

DADDI rt, rs, immediate

Purpose:

To add a constant to a 64-bit integer. If overflow occurs, then trap.

Implementation:

rt = rs + immediate

How to decode:

Opcode:

25

Format:

DADDIU rt, rs, immediate

Purpose:

To add a constant to a 64-bit integer.

Implementation:

rt = rs + immediate

How to decode:

Opcode:

0

Format:

DADDU rd, rs, rt

Purpose:

To add 64-bit integers.

Implementation:

rd = rs + rt

How to decode:

Opcode:

0

Format:

DDIV rs, rt

Purpose:

To divide 64-bit signed integers.

Implementation:

LO = rs / rt; HI = rs MOD rt

How to decode:

Opcode:

0

Format:

DDIVU rs, rt

Purpose:

To divide 64-bit unsigned integers.

Implementation:

LO = rs / rt; HI = rs MOD rt

How to decode:

Opcode:

0

Format:

DIV rs, rt

Purpose:

To divide 32-bit signed integers.

Implementation:

LO = rs / rt; HI = rs MOD rt

How to decode:

Opcode:

0

Format:

DIVU rs, rt

Purpose:

To divide 32-bit unsigned integers.

Implementation:

LO = rs / rt; HI = rs MOD rt

How to decode:

Opcode:

0

Format:

DMULT rs, rt

Purpose:

To multiply 64-bit signed integers.

Implementation:

LO = low(rs*rt); HI = high(rs*rt)

How to decode:

Opcode:

0

Format:

DMULTU rs, rt

Purpose:

To multiply 64-bit unsigned integers.

Implementation:

LO = low(rs*rt); HI = high(rs*rt)

How to decode:

Opcode:

0

Format:

DSLL rd, rt, sa

Purpose:

To left shift a doubleword by a fixed amount -- 0 to 31 bits.

Implementation:

rd = rt << sa

How to decode:

Opcode:

0

Format:

DSLL32 rd, rt, sa

Purpose:

To left shift a doubleword by a fixed amount -- 32 to 63 bits.

Implementation:

rd = rt << (sa+32)

How to decode:

Opcode:

0

Format:

DSLLV rd, rt, rs

Purpose:

To left shift a doubleword by a variable number of bits.

Implementation:

rd = rt << rs

How to decode:

Opcode:

0

Format:

DSRA rd, rt, sa

Purpose:

To arithmetic right shift a doubleword by a fixed amount -- 0 to 31 bits.

Implementation:

rd = rt >> sa

How to decode:

Opcode:

0

Format:

DSRA32 rd, rt, sa

Purpose:

To arithmetic right shift a doubleword by a fixed amount -- 32-63 bits.

Implementation:

rd = rt >> (sa+32)

How to decode:

Opcode:

0

Format:

DSRAV rd, rt, rs

Purpose:

To arithmetic right shift a doubleword by a variable number of bits.

Implementation:

rd = rt >> rs

How to decode:

Opcode:

0

Format:

DSRL rd, rt, sa

Purpose:

To logical right shift a doubleword by a fixed amount -- 0 to 31 bits.

Implementation:

rd = rt >> sa

How to decode:

Opcode:

0

Format:

DSRL32 rd, rt, sa

Purpose:

To logical right shift a doubleword by a fixed amount -- 32 to 63 bits.

Implementation:

rd = rt >> (sa+32)

How to decode:

Opcode:

0

Format:

DSRLV rd, rt, rs

Purpose:

To logical right shift a doubleword by a variable number of bits.

Implementation:

rd = rt >> rs

How to decode:

Opcode:

0

Format:

DSUB rd, rs, rt

Purpose:

To subtract 64-bit integers; trap if overflow.

Implementation:

rd = rs - rt

How to decode:

Opcode:

0

Format:

DSUBU rd, rs, rt

Purpose:

To subtract 64-bit integers.

Implementation:

rd = rs - rt

How to decode:

Opcode:

15

Format:

LUI rt, immediate

Purpose:

To load a constant into the upper half of a word.

Implementation:

rt = immediate * 10000h

How to decode:

Opcode:

0

Format:

MFHI rd

Purpose:

To copy the special purpose HI register to a GPR.

Implementation:

rd = HI

How to decode:

Opcode:

0

Format:

MFLO rd

Purpose:

To copy the special purpose LO register to a GPR.

Implementation:

rd = LO

How to decode:

Opcode:

0

Format:

MTHI rs

Purpose:

To copy a GPR to the special purpose HI register.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

0

Format:

MTLO rs

Purpose:

To copy a GPR to the special purpose LO register.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

0

Format:

MULT rs, rt

Purpose:

To multiply 32-bit signed integers.

Implementation:

LO = low(rs*rt); HI = high(rs*rt)

How to decode:

Opcode:

0

Format:

MULTU rs, rt

Purpose:

To multiply 32-bit unsigned integers.

Implementation:

LO = low(rs*rt); HI = high(rs*rt)

How to decode:

Opcode:

0

Format:

NOR rd, rs, rt

Purpose:

To do a bitwise logical NOT OR.

Implementation:

rd = (rs NOR rt)

How to decode:

Opcode:

0

Format:

OR rd, rs, rt

Purpose:

To do a bitwise logical OR.

Implementation:

rd = (rs OR rt)

How to decode:

Opcode:

13

Format:

ORI rt, rs, immediate

Purpose:

To do a bitwise logical OR with a constant. Comment: ORI rt, r0, imm is equal to a LI rt, imm

Implementation:

rt = (rs OR immediate)

How to decode:

Opcode:

0

Format:

SLL rd, rt, sa

Purpose:

To left shift a word by a fixed number of bits. Comment: SLL r0, r0, 0 is equal to a NOP (No OPeration)

Implementation:

rd = rt << sa

How to decode:

Opcode:

0

Format:

SLLV rd, rt, rs

Purpose:

To left shift a word by a variable number of bits.

Implementation:

rd = rt << sa

How to decode:

Opcode:

0

Format:

SLT rd, rs, rt

Purpose:

To record the result of a less-than comparison.

Implementation:

if rs < rt then rd = 1 else rd = 0

How to decode:

Opcode:

10

Format:

SLTI rt, rs, immediate

Purpose:

To record the result of a less-than comparison with a constant.

Implementation:

if rs < immediate then rd = 1 else rd = 0

How to decode:

Opcode:

11

Format:

SLTIU rt, rs, immediate

Purpose:

To record the result of an unsigned less-than comparison with a constant.

Implementation:

if rs < immediate then rd = 1 else rd = 0

How to decode:

Opcode:

0

Format:

SLTU rd, rs, rt

Purpose:

To record the result of an unsigned less-than comparison.

Implementation:

if rs < rt then rd = 1 else rd = 0

How to decode:

Opcode:

0

Format:

SRA rd, rt, sa

Purpose:

To arithmetic right shift a word by a fixed number of bits.

Implementation:

rd = rt >> sa

How to decode:

Opcode:

0

Format:

SRAV rd, rt, rs

Purpose:

To arithmetic right shift a word by a variable number of bits.

Implementation:

rd = rt >> rs

How to decode:

Opcode:

0

Format:

SRL rd, rt, sa

Purpose:

To logical right shift a word by a fixed number of bits.

Implementation:

rd = rt >> sa

How to decode:

Opcode:

0

Format:

SRLV rd, rt, rs

Purpose:

To logical right shift a word by a variable number of bits.

Implementation:

rd = rt >> rs

How to decode:

Opcode:

0

Format:

SUB rd, rs, rt

Purpose:

To subtract 32-bit integers. If overflow occurs, then trap. Comment: SUB rd, r0, rt is equal to a NEG rd, rt

Implementation:

rd = rs - rt

How to decode:

Opcode:

0

Format:

SUBU rd, rs, rt

Purpose:

To subtract 32-bit integers. No trap on overflow. Comment: SUBU rd, r0, rs is equal to a NEGU rd, rs

Implementation:

rd = rs - rt

How to decode:

Opcode:

0

Format:

XOR rd, rs, rt

Purpose:

To do a bitwise logical EXCLUSIVE OR.

Implementation:

rd = (rs XOR rt)

How to decode:

Opcode:

14

Format:

XORI rt, rs, immediate

Purpose:

To do a bitwise logical EXCLUSIVE OR with a constant.

Implementation:

rd = (rs XOR immediate)

How to decode:

Opcode:

4

Format:

BEQ rs, rt, offset

Purpose:

To compare GPRs then do a PC-relative conditional branch. Comment: BEQ rs, r0, offset is equal to a BEQZ rs, offset BEQ r0, r0, offset is equal to a B offset

Implementation:

branch if rs = rt

How to decode:

Opcode:

20

Format:

BEQL rs, rt, offset

Purpose:

To compare GPRs then do a PC-relative conditional branch; execute the delay slot only if the branch is taken. Comment: BEQL rs, r0, offset is equal to a BEQZL rs, offset

Implementation:

branch if rs = rt

How to decode:

Opcode:

1

Format:

BGEZ rs, offset

Purpose:

To test a GPR then do a PC-relative conditional branch.

Implementation:

branch if rs >= 0 (signed)

How to decode:

Opcode:

1

Format:

BGEZAL rs, offset

Purpose:

To test a GPR then do a PC-relative conditional procedure call. Comment: BGEZAL r0, offset is equal to a BAL offset

Implementation:

branch if rs >= 0 (signed) (return address in ra)

How to decode:

Opcode:

1

Format:

BGEZALL rs, offset

Purpose:

To test a GPR then do a PC-relative conditional procedure call; execute the delay slot only if the branch is taken.

Implementation:

branch if rs >= 0 (signed) (return address in ra)

How to decode:

Opcode:

1

Format:

BGEZL rs, offset

Purpose:

To test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.

Implementation:

branch if rs >= 0 (signed)

How to decode:

Opcode:

7

Format:

BGTZ rs, offset

Purpose:

To test a GPR then do a PC-relative conditional branch.

Implementation:

branch if rs > 0 (signed)

How to decode:

Opcode:

23

Format:

BGTZL rs, offset

Purpose:

To test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.

Implementation:

branch if rs > 0 (signed)

How to decode:

Opcode:

6

Format:

BLEZ rs, offset

Purpose:

To test a GPR then do a PC-relative conditional branch.

Implementation:

branch if rs <= 0 (signed)

How to decode:

Opcode:

22

Format:

BLEZL rs, offset

Purpose:

To test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.

Implementation:

branch if rs <= 0 (signed)

How to decode:

Opcode:

1

Format:

BLTZ rs, offset

Purpose:

To test a GPR then do a PC-relative conditional branch.

Implementation:

branch if rs < 0 (signed)

How to decode:

Opcode:

1

Format:

BLTZAL rs, offset

Purpose:

To test a GPR then do a PC-relative conditional procedure call.

Implementation:

branch if rs < 0 (signed) (return address in ra)

How to decode:

Opcode:

1

Format:

BLTZALL rs, offset

Purpose:

To test a GPR then do a PC-relative conditional procedure call; execute the delay slot only if the branch is taken.

Implementation:

branch if rs < 0 (signed) (return address in ra)

How to decode:

Opcode:

1

Format:

BLTZL rs, offset

Purpose:

To test a GPR then do a PC-relative conditional branch; execute the delay slot only if the branch is taken.

Implementation:

branch if rs < 0 (signed)

How to decode:

Opcode:

5

Format:

BNE rs, rt, offset

Purpose:

To compare GPRs then do a PC-relative conditional branch. Comment: BNE rs, r0, offset is equal to a BNEZ rs, offset

Implementation:

branch if rs <> rt

How to decode:

Opcode:

21

Format:

BNEL rs, rt, offset

Purpose:

To compare GPRs then do a PC-relative conditional branch; execute the delay slot only if the branch is taken. Comment: BNEL rs, r0, offset is equal to a BNEZL rs, offset

Implementation:

branch if rs <> rt

How to decode:

Opcode:

2

Format:

J target

Purpose:

To branch within the current 256 MB aligned region.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

3

Format:

JAL target

Purpose:

To procedure call within the current 256 MB aligned region.

Implementation:

return address in ra

How to decode:

Opcode:

0

Format:

JALR rs, rd

Purpose:

To procedure call to an instruction address in a register.

Implementation:

return address in rd

How to decode:

Opcode:

0

Format:

JR rs

Purpose:

To branch to an instruction address in a register.

Implementation:

PC = rs

How to decode:

Opcode:

0

Format:

BREAK offset

Purpose:

To cause a Breakpoint exception.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

0

Format:

SYSCALL offset

Purpose:

To cause a System Call exception.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

0

Format:

TEQ rs, rt

Purpose:

To compare GPRs and do a conditional Trap.

Implementation:

if rs = rt then trap

How to decode:

Opcode:

1

Format:

TEQI rs, immediate

Purpose:

To compare a GPR to a constant and do a conditional Trap.

Implementation:

if rs = immediate then trap

How to decode:

Opcode:

0

Format:

TGE rs, rt

Purpose:

To compare GPRs and do a conditional Trap.

Implementation:

if rs >= rt then trap

How to decode:

Opcode:

1

Format:

TGEI rs, immediate

Purpose:

To compare a GPR to a constant and do a conditional Trap.

Implementation:

if rs >= immediate then trap

How to decode:

Opcode:

1

Format:

TGEIU rs, immediate

Purpose:

To compare a GPR to a constant and do a conditional Trap.

Implementation:

if rs >= immediate then trap

How to decode:

Opcode:

0

Format:

TGEU rs, rt

Purpose:

To compare GPRs and do a conditional Trap.

Implementation:

if rs >= rt then trap

How to decode:

Opcode:

0

Format:

TLT rs, rt

Purpose:

To compare GPRs and do a conditional Trap.

Implementation:

if rs < rt then trap

How to decode:

Opcode:

1

Format:

TLTI rs, immediate

Purpose:

To compare a GPR to a constant and do a conditional Trap.

Implementation:

if rs < immediate then trap (signed)

How to decode:

Opcode:

1

Format:

TLTIU rs, immediate

Purpose:

To compare a GPR to a constant and do a conditional Trap.

Implementation:

if rs < immediate then trap

How to decode:

Opcode:

0

Format:

TLTU rs, rt

Purpose:

To compare GPRs and do a conditional Trap.

Implementation:

if rs < rt then trap

How to decode:

Opcode:

0

Format:

TNE rs, rt

Purpose:

To compare GPRs and do a conditional Trap.

Implementation:

if rs <> rt then trap

How to decode:

Opcode:

1

Format:

TNEI rs, immediate

Purpose:

To compare a GPR to a constant and do a conditional Trap.

Implementation:

if rs <> immediate then trap

How to decode:

Opcode:

47

Format:

CACHE op, offset(base)

Purpose:

The 16-bit offset is sign-extended and added to the contents of general register base to form a virtual address. The virtual address is translated to a physical address using the TLB, and the 5-bit sub-opcode specifies a cache operation for that address.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10000

Format:

ERET

Purpose:

ERET is the R4300 instruction for returning from an interrupt,

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10000

Format:

MFC0 rt, rd

Purpose:

To copy a word from an FPR to a GPR.

Implementation:

rt = COP rd

How to decode:

Opcode:

10000

Format:

MTC0 rt, rd

Purpose:

To copy a word from a GPR to an FPR.

Implementation:

COP rd = rt

How to decode:

Opcode:

10000

Format:

TLBP

Purpose:

The Index register is loaded with the address of the TLB entry

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10000

Format:

TLBR

Purpose:

The G bit (which controls ASID matching) read from the TLB is

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10000

Format:

TLBWI

Purpose:

The G bit of the TLB is written with the logical AND of the G bits

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10000

Format:

TLBWR

Purpose:

The G bit of the TLB is written with the logical AND of the G bits

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

ABS.S fd, fs ABS.D fd, fs

Purpose:

To compute the absolute value of an FP value.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

ADD.S fd, fs, ft ADD.D fd, fs, ft

Purpose:

To add FP values.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

BC1F offset

Purpose:

To test an FP condition code and do a PC-relative conditional branch.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

BC1FL offset

Purpose:

To test an FP condition code and do a PC-relative conditional branch; execute the delay slot only if the branch is taken

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

BC1T offset

Purpose:

To test an FP condition code and do a PC-relative conditional branch.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

BC1TL offset

Purpose:

To test an FP condition code and do a PC-relative conditional branch; execute the delay slot only if the branch is taken.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

C.cond.S fs, ft C.cond.D fs, ft

Purpose:

To compare FP values and record the Boolean result in

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

CEIL.L.S fd, fs CEIL.L.D fd, fs

Purpose:

To convert an FP value to 64-bit fixed-point, rounding up.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

CEIL.W.S fd, fs CEIL.W.D fd, fs

Purpose:

To convert an FP value to 32-bit fixed-point, rounding up.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

CFC1 rt, fs

Purpose:

To copy a word from an FPU control register to a GPR.

Implementation:

rt = fs

How to decode:

Opcode:

10001

Format:

CTC1 rt, fs

Purpose:

To copy a word from a GPR to an FPU control register.

Implementation:

fs = rt

How to decode:

Opcode:

10001

Format:

CVT.D.S fd, fs CVT.D.W fd, fs CVT.D.L fd, fs

Purpose:

To convert an FP or fixed-point value to double FP.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

CVT.L.S fd, fs CVT.L.D fd, fs

Purpose:

To convert an FP value to a 64-bit fixed-point.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

CVT.S.D fd, fs CVT.S.W fd, fs CVT.S.L fd, fs

Purpose:

To convert an FP or fixed-point value to single FP.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

CVT.W.S fd, fs CVT.W.D fd, fs

Purpose:

To convert an FP value to 32-bit fixed-point.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

DIV.S fd, fs, ft DIV.D fd, fs, ft

Purpose:

To divide FP values.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

DMFC1 rt, fs

Purpose:

To copy a doubleword from an FPR to a GPR.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

DMTC1 rt, fs

Purpose:

To copy a doubleword from a GPR to an FPR.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

FLOOR.L.S fd, fs FLOOR.L.D fd, fs

Purpose:

To convert an FP value to 64-bit fixed-point, rounding down.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

FLOOR.W.S fd, fs FLOOR.W.D fd, fs

Purpose:

To convert an FP value to 32-bit fixed-point, rounding down.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

53

Format:

LDC1 ft, offset(base)

Purpose:

To load a doubleword from memory to an FPR.

Implementation:

COP ft = doubleword[base+offset]

How to decode:

Opcode:

49

Format:

LWC1 ft, offset(base)

Purpose:

To load a word from memory to an FPR. Comment: LWC1 ft, offset(base) is equal to a L.S ft, offset(base)

Implementation:

COP ft = word[base+offset]

How to decode:

Opcode:

10001

Format:

MFC1 rt, fs

Purpose:

To copy a word from an FPU (CP1) general register to a GPR.

Implementation:

rt = COP fs

How to decode:

Opcode:

10001

Format:

MOV.S fd, fs MOV.D fd, fs

Purpose:

To move an FP value between FPRs.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

MTC1 rt, fs

Purpose:

To copy a word from a GPR to an FPU (CP1) general register.

Implementation:

COP fs = rt

How to decode:

Opcode:

10001

Format:

MUL.S fd, fs, ft MUL.D fd, fs, ft

Purpose:

To multiply FP values.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

NEG.S fd, fs NEG.D fd, fs

Purpose:

To negate an FP value.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

ROUND.L.S fd, fs ROUND.L.D fd, fs

Purpose:

To convert an FP value to 64-bit fixed-point, rounding to nearest.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

ROUND.W.S fd, fs ROUND.W.D fd, fs

Purpose:

To convert an FP value to 32-bit fixed-point, rounding to nearest.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

61

Format:

SDC1 ft, offset(base)

Purpose:

To store a doubleword from an FPR to memory.

Implementation:

doubleword[base+offset] = COP rt

How to decode:

Opcode:

10001

Format:

SQRT.S fd, fs SQRT.D fd, fs

Purpose:

To compute the square root of an FP value.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

SUB.S fd, fs, ft SUB.D fd, fs, ft

Purpose:

To subtract FP values.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

57

Format:

SWC1 ft, offset(base)

Purpose:

To store a word from an FPR to memory. Comment: SWC1 ft, offset(base) is equal to a S.S ft, offset(base)

Implementation:

word[base+offset] = COP rt

How to decode:

Opcode:

10001

Format:

TRUNC.L.S fd, fs TRUNC.L.D fd, fs

Purpose:

To convert an FP value to 64-bit fixed-point, rounding toward zero.

Implementation:

Nothing or missing documentation

How to decode:

Opcode:

10001

Format:

TRUNC.W.S fd, fs TRUNC.W.D fd, fs

Purpose:

To convert an FP value to 32-bit fixed-point, rounding toward zero.

Implementation:

Nothing or missing documentation

How to decode: